1. Field of the Invention
The present invention relates to a stack gate flash memory, and more particularly, to a semiconductor memory and a method for fabricating the same, in which sides of a floating gate is formed to have a streamlined profile, for improving a device performance.
2. Background of the Related Art
In general, a stack gate flash memory is a nonvolatile memory having a stack of a floating gate for storage of electrons and a control gate for providing a bias in data storage and forwarding. A related art stack gate flash memory will be explained with reference to the attached drawings. FIG. 1 illustrates a layout of a related art flash memory cell, and FIGS. 2A.about.2E illustrate sections across lines X-X', Y1-Y1', and Y2-Y2' in FIG. 1 showing the steps of a method for fabricating a flash memory cell.
In the related art method for fabricating a stack gate flash memory cell, after an etch profile of the floating gate is formed in a vertical direction, a polysilicon layer for forming an ONO layer and a control gate is formed. In a plan view as shown in FIG. 1, the floating gate 3b and the control gate 5a are formed to cross each other (before patterning the floating gate for the second time). The floating gate 3b is patterned in a direction the same with a field oxide film 6 for the first time, and etched self-aligned with the control gate again after the control gate 5a is patterned, thereby being floated electrically. The `A` in FIG. 1 denotes a part removed in the second patterning for forming the floating gate, and the `B` denotes a part of the field oxide film damaged when the field oxide film is overetched for removal of an ONO stringer remained in a vertical direction at sides of a patterned layer after the first patterning for forming the floating gate.
A related art method for fabricating a stack gate flash memory will be explained. FIGS. 2A.about.2E illustrate sections showing the steps of a related art method for fabricating a stack gate flash memory, wherein positions of the sections are determined such that the sections show the best features of the steps.
Referring to FIG. 2A, a field oxide film 6 is formed on a device isolation region of a semiconductor substrate, and a tunneling oxide film 2 is formed on an active region of the semiconductor substrate 1. A material layer for forming a floating gate, such as polysilicon layer, is formed on an entire surface having the tunneling oxide film 2 formed thereon. Then, as shown in FIG. 2B, photolithography is used in a first patterning, to form a polysilicon pattern layer 3a for forming a floating gate. As shown in FIGS. 2C and 2C-1, an ONO (Oxide-Nitride-Oxide) layer 4 as an interlayer insulating film, and a material layer for forming a control gate, such as a polysilicon layer 5, are formed on an entire surface having the polysilicon pattern layer 3a formed thereon. In this instance, an X-X' section shows a state in which the tunneling oxide film 2, the polysilicon pattern layer 3a, the ONO layer 4, and the polysilicon layer 5 are formed on the semiconductor substrate 1 stacked in succession. Then, as shown in FIG. 2D, the polysilicon layer 5 for forming the control gate is etched selectively, to form the control gate 5a, and the control gate 5a is used as a mask in etching the ONO layer 4, and the polysilicon pattern layer 3a selectively, to stack the control gate 5a, the ONO layer 4, and the floating gate 3a in succession. In this instance, the etching of the polysilicon pattern layer 3a using the control gate 5a as a mask is conducted as shown in FIGS. 2D-1, 2D-2, and 2D-3. That is, an overetch is conducted to remove remained vertical stringers 4a of the ONO layer at sides of the polysilicon pattern layer 3a in a Y2-Y2' section, though there are no such vertical stringers in an X-X1' section. The overetch gives damage to the field oxide film 6(`C` part). Then, as shown in FIG. 2E, impurity ions are implanted in surfaces of the substrate on both sides of the control gate 5a and the gate sidewalls 7 using the control gate 5a and the gate sidewalls 7 as masks, to form source/drain regions 8. The flash memory cell formed according to this process is a nonvolatile memory operative in write/erase/read. In writing, high voltages are provided to the control gate 5a and a drain, for injecting hot electrons generated in the vicinity of the drain to the floating gate 3b. The electrons injected in the floating gate 3b boosts a threshold voltage of the control gate, to form a state which is different from a low threshold voltage state. The electrons injected in the floating gate 3b stay in the floating gate 3b even if there is no external power supply, to maintain a programmed state. In erasing, a high voltage is provided to a source junction, so that the electrons in the floating gate 3b escape to the source junction through the tunneling oxide film 2. The escape of the electrons form the floating gate 3b drops the threshold voltage of the control gate 5a. In reading, a voltage in the middle of the threshold voltage in the erase state and the threshold voltage in the programming state is provided to the control gate 5a, and the channel is determined of being conductive. In the programmed state, the channel is not conductive as the threshold voltage is lower than a voltage provided to the control gate 5a, and, in the erase state, the channel is conductive as the threshold voltage is lower than a control gate 5a voltage.
However, the related art stack gate flash memory has the following problems.
First, the vertical sides of the floating gate (`a` part in FIG. 2C) cause difficulty in removing vertical ONO layers remained at sides of the floating gate. The ONO layer (at sides of the floating gate) for use as an interlayer insulating layer remained even after the polysilicon for use as the floating gate is etched makes following processes difficult, and is a cause of defect as the ONO layer falls off during the following processes. The overetch carried out in an intention to remove the remained ONO layer which causes the defect completely causes damage to the field oxide film as an etch selectivity of the ONO layer over the field oxide film is not so high. When the floating gate has a thickness in a range of 1500 .ANG., as the ONO layer also has a thickness in the range of 1500 .ANG., a loss of the field oxide film is in the range. Such as loss of field oxide film deteriorates a device isolation characteristics, and causes difficulty in processing the fabrication coming form formation of steps. And, the damage to the active region coming from the overetch affects to a device reliability.
Second, the leakage of electrons from sharp edges of the floating gate when a high voltage is provided to the control gate in a programming operation deteriorates a data retention characteristics.
Third, though a program efficiency can be the better as an area of the floating gate overlapped with the control gate on the field oxide film the larger owing to an increased coupling ratio, a distance between the floating gates is dependent on a minimum patterning dimension in a photolithography as the first time etching of the floating gate is carried out by the photolithography. There is a limitation in increasing an area of the floating gate in the same area.